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All Courses
Technology
VLSI design
Curriculum
6 Sections
34 Lessons
18 Weeks
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Module1: Getting familiar with VLSI
5
6.1
Introduction to VLSI
6.2
ASIC flow
6.3
Different fields in VLSI
6.4
Manufacturing process of an IC
6.5
Understanding various chips (mobile, AI server, network, smart watch etc.,)
Module2: Basics of Physical design.
4
7.1
physical design flow.
7.2
Inputs and outputs of physical design.
7.3
Introduction to Industry standard tools.
7.4
Synthesis (RTL to Netlist)
Module3: Static timing analysis
6
8.1
Data paths & Explaining SDC.
8.2
Understanding different timing checks. (setup, Hold, Recovery, Removal)
8.3
Timing Exceptions.
8.4
Timing fixes.
8.5
Derates (OCV, AOCV, POCV and LVF)
8.6
PVT and corners
Module 4: Sanity checks, Floorplaning & Power planning
5
9.1
Sanity checks and fixes
9.2
Floorplaning basics and Macro placement
9.3
Preplace/Physical cells and their placement requirements.
9.4
Introduction to metals & tracks
9.5
How to design and quantify a power grid for chip?
Module5: Placement and Clock tree synthesis.
8
10.1
Introduction to Placement.
10.2
Stages and Goals of placement.
10.3
Congestion, Timing issues and resolutions at placement.
10.4
Intro to CTS
10.5
Types of CTS and trade-off with power, performance and area.
10.6
Clock tree routing and cell usage.
10.7
Clock tree reports validation.
10.8
Methods to fix Latency and skew.
Module 6: Routing and Extraction
6
11.1
Stages in Routing
11.2
Introduction to crosstalk (SI)
11.3
Avoiding SI effects and fixes
11.4
Intro to DRCs and fixes.
11.5
R & C Extraction.
11.6
Introduction to Physical verification.
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